1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to a method for electrically identifying mask vintages in semiconductor memory modules.
2. Description of Related Art
Mask identification remains important to several areas of design and manufacturing. In the design of semiconductor components, each design update requires confirmation that the correct mask vintages were used. This can be achieved by characterizing the exact vintage of each chip/module being tested. In manufacturing testing, the ability to separate different chip vintages facilitates identifying the pedigree of the devices under test for subsequent investigation. Similarly, in engineering failure analysis, the ability to know the mask vintage without resorting to visual identification remains beneficial to the investigating engineer.
After processing, testing, and packaging, it is difficult to keep track of particular mask changes and variations from lot to lot, or wafer to wafer. Typically, paper records of changes are employed to maintain the current status of each mask, however, these records often remain incomplete, requiring significant cost to keep current.
Visual mask marks, added to the surface of memory chips, have been used for a number of years to identify the mask vintage of fabricated semiconductor devices. This visual method, however, is only successful if the surface of the chip remains visible throughout the chip""s fabrication.
Other methods, such as etching the surface of the semiconductor wafer to form visibly identifiable characters, have also been employed for the purpose of identifying the fabrication status of the wafer.
Recent advances in characterizing semiconductor dies have been realized using electrical identification. In some instances, fusible links have been used in a readable binary fashion for coding the status of semiconductor devices.
Methods to electrically interrogate a test circuit on a semiconductor chip containing fabrication information have become more prevalent due, in part, to their ability to encode more information within a smaller area of the die. Additionally, different types of electrical identification methods have been introduced which are more adaptable to accommodating the numerous changes during the device fabrication process. For example, in U.S. Pat. No. 4,419,747 issued to Jordan on Dec. 6, 1983, entitled, xe2x80x9cMETHOD AND DEVICE FOR PROVIDING PROCESS AND TEST INFORMATION IN SEMICONDUCTORS,xe2x80x9d a memory array on the chip is modified to include processing and test information. The array is typically a non-volatile EEPROM type, however, fusible-link devices or laser blown fuses are also known in the art for such construction. With this technique, product information disclosed may include fabrication lot number, wafer number, and the array location within the die, referred to as the die position number. Although not a common practice, mask vintages may also be recorded using this technique since the binary encoded format is capable of alternative designations. However, in all of the above fuse or array constructions, the components are fabricated separately, from technologies other than those used to fabricate the mask, thus requiring extra process steps during fabrication.
Similarly, in U.S. Pat. No. 5,642,307 issued to Jernigan on Jun. 24, 1997, entitled, xe2x80x9cDIE IDENTIFIER AND DIE IDENTIFICATION METHOD,xe2x80x9d an identification section is fabricated onto a semiconductor that includes structure for storing and reading die-specific information that characterizes the particular integrated circuit. The structure for storing is a memory section, typically non-volatile, or may also be fuse-programmable. An enabling circuit initiates the reading structure for interrogating the memory or fuse devices. Although capable of designating mask vintage information, this method requires additional device fabrication of various technologies to employ the memory or fuse-programmable circuitry necessary to retain the semiconductor fabrication status information. Thus, there remains a need in the art to reduce the complexity associated with encoding semiconductor fabrication information on a device, and especially for encoding mask vintage information.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of identifying unique design characteristics of semiconductor mask levels.
It is another object of the present invention to provide an identification section on a semiconductor device for storing die specific information using the available mask technology.
A further object of the invention is to provide an inexpensive, reliable device for providing identification of design characteristics and other key parameters of semiconductors.
It is yet another object of the present invention to provide a method, whereby mask vintage information for a semiconductor device may be obtained through electrical interrogation of the device.
Still other advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method for identifying design characteristics of a semiconductor device, comprising the steps of: a) providing the semiconductor device having a plurality of semiconductor levels of different semiconductor technologies; and, b) forming electrical devices from each of the semiconductor technologies within each of the semiconductor levels.
Additionally, step (b) comprises forming conduction paths made from the different semiconductor technologies.
The method may further comprise the steps of: c) encoding the electrical devices in a binary encoded format to identify the design characteristics; and, d) electrically interrogating the semiconductor device for the design characteristics by reading the binary encoded electrical devices.
Step (c) may further comprise changing the conduction paths such that electrical opens and shorts in the conduction paths provide the binary encoded format for identifying the design characteristics.
The present invention relates to, in a second aspect, a method for identifying mask vintage of a semiconductor device, comprising: a) providing a semiconductor substrate having a plurality of semiconductor layers with different semiconductor technologies; b) fabricating at least one conductor for each of the plurality of semiconductor layers using the semiconductor technology of each layer; c) encoding the at least one conductor in a binary encoded format to identify the mask vintage; and, d) electrically interrogating the semiconductor device for the mask vintage by reading the binary encoded conductors.
In a third aspect, the present invention relates to a method for identifying mask vintage of a deep trench and surface strap structure on a semiconductor device, comprising: a) providing a semiconductor substrate having a plurality of semiconductor layers of different semiconductor technologies; b) forming a conduction path of conductors for each layer of the deep trench and surface strap structure, wherein each of the conductors is fabricated from the semiconductor technology of each layer of the structure, the conduction path comprising: 1) connecting electrically conductive surface strap conductors on adjacent sides of the deep trench; 2) forming diffusion conductors for attachment to each of the surface strap conductors; 3) forming a first contact to each of the diffusion conductors; 4) electrically connecting noncontiguous first metal layer conductors to each of the first contacts; 5) forming a second contact to one of the first metal layer conductors; and, 6) forming a second metal layer conductor for electrical connection to the second contact; c) encoding the conduction path in a binary encoded format to identify the mask vintage; and, d) electrically interrogating the semiconductor device for the mask vintage by reading the binary encoded conduction path.
In addition, the surface strap conductors and the first contacts may be separated by a PFET transistor.
In a fourth aspect, the present invention relates to an apparatus for identifying the mask vintage of a semiconductor device, comprising: a semiconductor device having a plurality of semiconductor levels of different semiconductor technologies; and, electrical devices constructed from each of the semiconductor technologies within each of the semiconductor levels, wherein the electrical devices form a mask programmable conduction path within the semiconductor device.
Additionally this method further comprises: means for encoding the electrical devices in a binary encoded format to identify the mask vintage; and, means for electrically interrogating the semiconductor device for the mask vintage by reading the binary encoded electrical devices.
In a fifth aspect, the present invention relates to an apparatus for identifying the mask vintage of a deep trench and surface strap structure, comprising a mask programmable conduction path fabricated from the technology of each of the following layers: a first metal layer, a first contact layer, a diffusion layer, a surface strap layer, a deep trench layer, a second contact layer, and a second metal layer. The apparatus may further comprise a third contact layer and a third metal layer.
In a sixth aspect, the present invention relates to an apparatus for identifying the mask vintage of a polysilicon gate structure, comprising a mask programmable conduction path fabricated from the technology of each of the following layers: a first metal layer, a first contact layer, a polysilicon gate layer, a second contact layer, and a second metal layer.
In a seventh aspect, the present invention relates to an apparatus for identifying the mask vintage of N Well and N Diffusion Implant structures, comprising a mask programmable conduction path fabricated from the technology of each of the following layers: a first metal layer, a first contact layer, a diffusion layer, a diffusion N Well layer, a second contact layer, and a second metal layer.
In an eighth aspect, the present invention relates to an apparatus for identifying the mask vintage of a substrate P-diffusion structure, comprising a mask programmable conduction path fabricated from the technology of each of the following layers: a first metal layer, a first contact layer, and a P diffusion layer.
In a ninth aspect, the present invention relates to an apparatus for identifying the mask vintage of a diffusion structure, first and second metal structures, first and second contact structures, comprising a mask programmable conduction path fabricated from the technology of each of the following layers: a first metal layer, a first contact layer, a polysilicon gate layer, a diffusion layer, a second contact layer, and a second metal layer.